C = s wl/t (1.2)
where s is the relative permittivity and t is the thickness of the insulator. The total RC
delay can be given by
RC= p 1/wd s wl/t =ps 12/td (1.3)
Thus, it can be seen from Eq. (1.3) that RC delay is independent of the line width
and further scaling of line width translates into reduction of IC line thickness which in
turn increases the RC delay. Other factors such as parasitic capacitances and cross-talk
become dominant for sub 0.5 |tm integrated circuits. One approach to decrease the RC
delay is by incorporating metals of low resistivity, and interlayer dielectrics of lower
dielectric constant. Table 1-1 gives the simple RC time constants calculated for a few
metals of given Rs (sheet resistance) and 1 mm length on 1 tm thick SiO2 [9]. The other
approach implemented widely in the industry is forming multilevel metallization schemes
where different levels of metal interconnections are isolated by dielectrics and are
connected by vertical vias.
Table 1-1. Interconnection delay (RC) in silicon VLSI chip.
Metal Bulk Polycrystalline Film Rs Delay'
resistivity film resistivity thickness (Q /square) (ps/mm)
(l2 cm) (S2 cm) (A)
Polysilicon -1000 5000 20 690
CoSi2 10 15 2500 0.6 21
MoSi2 -35 -100 2500 4 138
TaSi2 45 55 2500 2.2 76
TiSi2 13 15 2500 0.6 21
WSi2 -25 70 2500 2.8 97
W 5.65 8-10 2500 0.32-0.4 11-14
Mo 5.2 8-10 2500 0.32-0.4 11-14
Al 2.65 2.7 2500 0.11 4
Cu 1.67 2.0 2500 0.08 3
'Delay=RC=34.5 Rs (ps/mm) for 1 mm length conductor on l[tm thick SiO2 [10].