6.2 Fabrication Procedure

     The overall pattern is fabricated on a square silicon chip 200 mils on a side where six mask levels are used [68]. The masks were used in the following sequence: base, emitter, base contact, gate oxide, contact and metal. Appropriate cleaning procedures (see Appendix A) precede the ,diffusion of impurities, and a negative photoresist process was used in the masking steps. The base mask delineates regions whose conductivity type is opposite from that of the collector substrate, and the emitter mask delineates regions whose conductivity type is the same as that of the collector substrate. A base region approximately two pm deep is diffused into the background material; then the emitter region is diffused into the base to a depth of approximately one im. The base contact mask is used to open windows onto the base region, where an n+ diffusion is made to improve ohmic contact to the base. The gate oxide mask delineates regions where an oxide layer of closely controlled thickness is grown to serve as a gate for MOS devices. After front-side metallization, a portion of the wafer was separated. This section was, scribed to provide the Hall effect devices. The remainder of the wafer was then metallized on the backside and alloyed. After scribing, the devices were mounted on TO-5 headers, metal contact bonding was made, and the devices were encapsulated. A layer of ceramic insulating material was used to isolate the devices from contact with the header. Resistivity measurements were then made to select devices for use in this study.